The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device with an increased channel length as well as an increased channel width and a method for manufacturing the same.
As design rules of semiconductor devices are rapidly decreased, channel length and width of a transistor are correspondingly decreased. Accordingly, leakage current is increased due to the decreased channel length and as a consequence desired carrier mobility cannot be ensured.
In existing planar channel structures, a method of improving the mobility of the channel should be used to increase the carrier mobility. Accordingly, a method of using strained silicon or silicon germanium (SiGe) as a channel material for improving the mobility of the channel and a method in which the channel is made into a pin shape for increasing the carrier mobility have been suggested.
A process for removing some of the thickness of an isolation layer is required to form the pin shaped channel. However, with decreases in the size of a device, a phenomenon occurs in that an insulation layer for an isolation layer filled in a trench has non-uniform properties over each portion in the trench. Accordingly, portions of the insulation layer having weak etching properties are exposed during a process of removing the isolation layer. This results in a new problem caused by the non-uniform etching speed.
To solve these problems, a method of forming a recess channel structure has been suggested. The recess channel structure is more stable during processing than the method of forming a pin shaped channel. In the recess channel structure, an increase in the channel length leads to improved device properties. The application of the recess channel structure has recently been introduced into the spotlight.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device having a recess channel structure. The left drawing is a sectional view taken along a direction of the channel width and the right is a sectional view taken along a direction of the channel length.
In FIG. 1, isolation layers 102 are formed in a semiconductor substrate 100. The isolation layers 102 define active regions 100a. A channel portion in the active region 100a is recessed, and a gate 110 is formed over the channel portion in the recessed active region 100a. The gate 110 includes a gate insulation layer 104 formed over the surface of the recessed channel portion, a gate conductive layer 106 formed over the gate insulation layer 104, and a gate hard mask 108 formed over the gate conductive layer 106.
However, as shown in FIG. 1, while the channel length is increased in a conventional semiconductor device having the recess channel structure described above, the channel width remains unchanged. The channel width typically becomes narrower when the device size is decreased, and thus there is a limitation in ensuring the device properties.
A method has been suggested in which the recess channel structure is combined with the method of forming a pin shaped channel. In this method, the desired device properties are expected to be obtained since the channel length and the channel width can be increased.
However, this method is rarely utilized because of the difficulty in implementing both a process for filling an insulation layer for an isolation layer and an etching process for forming a pin gate.